1. Field of the Invention
The present invention relates to the field of semiconductor devices and more specifically to controlling short-channel effects in multi-gate devices.
2. Discussion of Related Art
During the past two decades, the physical dimensions of MOSFETs have been aggressively scaled for low-power, high-performance applications. The need for faster switching transistors requires shorter channel lengths. The continued decreasing size and need for low-power transistors makes overcoming the short channel effects of transistors necessary. However, as the dimensions of the transistors decrease the ability to control the leakage current becomes more difficult. To limit the amount of leakage current in a transistor current solutions involve strictly controlling the placement of the source and drain dopants within the active region of the transistor. Other techniques to combat the leakage current include implants in and around the channel such as halo and punchthrough implants. However, the use of such implants results in degraded performance of the transistor such as increasing the threshold voltage.
Multi-gate devices enable better control of the transistor channel than do planar transistors with a single gate. The use of more than one gate in the channel region of the transistor allows more control over the current flow within the channel. The better control over the channel minimizes short-channel effects. Despite the better control over the channel, the multi-gate devices are less efficient at controlling the electric fields from the source and drain regions. The electric fields from the source and drain regions result in short-channel effects such as an increased leakage current at a given gate voltage in the subthreshold region of device operation. As mentioned above, prior solutions to minimize this leakage current includes utilizing dopants in the channel that have unwanted effects such as increasing the threshold voltage of the transistor.